1. Field of the Invention
The present invention relates generally to a charge-transfer sense amplifier, and more particularly, to the structure of a charge-transfer sense amplifier available in a DRAM (Dynamic Random Access Memory) with a half Vcc precharge scheme, and an operating method therefor.
2. Description of the Prior Art
As a device for storing binary information, a random access memory employing a semiconductor has been known. The random access memory has a configuration as shown in FIG. 1, which is integrated on a semiconductor chip.
Referring to FIG. 1, a dynamic random access memory comprises a memory cell array MA comprising a plurality of memory cells for storing binary information. An address buffer AB generates an internal row address and an internal column address from an external address externally applied. A row decoder RD is responsive to the internal row address from the address buffer AB for selecting one row (a word line) from the memory cell array MA, and a column decoder CD is responsive to the internal column address from the address buffer AB for selecting one column (a pair of bit lines) from the memory cell array MA for memory cell selection. A sense amplifier and I/O gate (block S) comprises sense amplifiers for detecting and amplifying information in the memory cells connected to the word line selected by an output of a row decoder RD. An I/O gate is provided for connecting one column selected by an output of the column decoder CD to a data input/output bus I/O, and an output buffer OB is responsive to data on the data input/output bus I/O for applying output data D.sub.OUT to the exterior. An input buffer IB transmits input data D.sub.IN externally applied onto the data input/output bus I/O for accessing a selected memory. A control signal generator CG is also provided for generating signals for controlling an operation sequence of each circuit.
In FIG. 1, the bit lines (forming columns) included in the memory cell array MA have a folded bit line scheme, so that complementary data D and D appear on the data input/output bus I/O.
The external row address and the external column address are multiplexed, to be applied to the address buffer AB.
Each memory cell in such a DRAM has a one-device structure comprising one transistor and one capacitor. Binary information is stored in the capacitor in the form of electric charges.
In recent years, as the capacity of the DRAM is increased, the integration density on a chip is enhanced. The memory cell size is responsively scaled down. In this case, the number of memory cells connected to one bit line is increased so that the parasitic capacitance of the bit line is increased while the storage capacitance of the memory cell is decreased. As a result, the ratio C.sub.B /C.sub.S of the capacitance C.sub.B of the bit line to the storage capacitance C.sub.S of the memory cell becomes large. Consequently, a potential shift which appears on the bit line at the time of reading out information becomes smaller. Thus, a differential signal applied to a flip-flop type sense amplifier becomes smaller, so that the sense amplifier can not surely detect read information.
In order to compensate for such diminution of the differential signal in the large capacity DRAM, a charge-transfer sense amplifier has been proposed by L. G. Heller et al. See, for example, an article by L. G. Heller et al., entitled "High Sensitivity Charge-Transfer Sense Amplifier", IEEE Journal of Solid-State Circuits, Vol. SC-11, No. 5, October 1976, pp. 596-601.
FIG. 2 is a diagram of a structure of the charge-transfer sense amplifier, showing by way of example a pair of bit lines and portions related thereto.
The bit lines shown in FIG. 2 have a folded bit line configuration. More specifically, a first bit line 1a and a second bit line 1b are paired with each other, complementary data signals appearing on the bit lines.
A memory cell array MA includes a plurality of memory cells arranged in a matrix of rows and columns and dummy cells for providing a reference at the time of detecting data signals. In FIG. 2, two memory cells 2a and 2b are typically shown. Each of the memory cells comprises one transfer gate transistor and one storage capacitor. The memory cell 2a comprises a capacitor C4, a transistor Q11 and a word line WL1, and the memory cell 2b comprises a capacitor C3, a transistor Q12 and a word line WL2. A dummy cell 3a comprises a capacitor C1, a transistor Q9 and a dummy word line DWL1, and a dummy cell 3b comprises a capacitor C2, a transistor Q10 and a dummy word line DWL2. Capacitances of respective capacitors C1 and C2 in the dummy cells 3a and 3b are set to one-half of a capacitance of the storage capacitor, and information of an "L" level, i.e., 0 V is always stored in the capacitors C1 and C2 in the dummy cells 3a and 3 b. The transistor Q11 in the memory cell 2a and the transistor Q9 in the dummy cell 3a are connected to a first bit line 1a, and the transistor Q12 in the memory cell 2b and the transistor Q10 in the dummy cell 3b are connected to a second bit line 1b. The first bit line 1a and the second bit line 1b are in a complementary relation. However, both the first bit line 1a and the second bit line 1b are always precharged to the same potential Vcc in the initial stage of a read operation. C.sub.Ba denotes a parasitic capacitance of the first bit line 1a, and C.sub.Bb denotes a parasitic capacitance of the second bit line 1b.
A sense amplifier SA includes charge transfer elements Q3 and Q4 and a flip-flop type sense amplifier comprising cross-coupled transistors Q6 and Q7.
The charge transfer elements Q3 and Q4 provided on the bit lines 1a and 1b, respectively, comprise a MOS transistor. Each gate thereof is connected to a constant voltage supply V.sub.R1 (V.sub.R1 .apprxeq.Vcc+Vthn; Vthn denotes a threshold voltage of each of the transistors Q3 and Q4).
An equalize transistor Q5 responsive to a clock .phi.3 is provided between nodes N1 and N2.
In order to activate the flip-flop type sense amplifier, there is provided a MOS transistor Q8 responsive to a clock .phi.2 for grounding a node N3.
In order to precharge the nodes N1 and N2 to a predetermined potential V.sub.H (V.sub.H &gt;V.sub.C ; approximately 7 V), there are provided MOS transistors Q1 and Q2 responsive to a clock .phi.1, respectively. The high level of the clock .phi.1 satisfies the relation .phi.1h&gt;V.sub.H +Vthn.
The first node N1 has a parasitic capacitance C.sub.Sa, and the second node N2 has a parasitic capacitance C.sub.Sb.
The first and second bit lines 1a and 1b are connected to data input/output buses I/O and I/O through transfer gates T1 and T2 responsive to an output (a column decode signal) of a column decoder CD, respectively.
Referring now to the timing chart of FIG. 3, description is made of a read operation in the conventional charge-transfer sense amplifier.